Technical Field
The present invention relates to circuit design and analysis and, more particularly, to overlaying a circuit design on an image of the circuit.
Description of the Related Art
Performing tests, diagnostics, and failure analysis of modern integrated chips (ICs) often involves driving analytical tools by means of chip layout information so that appropriate locations may be probed, imaged, modified, etc. There are many such tools using a variety of different imaging techniques.
Chip design layout software is similarly varied. In general, layout tools are designed to show shapes that represent the different elements making up a circuit, such as metal lines, polysilicon gates, diffusions, contacts, etc. Different colors and layers may be used to indicate different parts of the circuit. Moreover, spatial coordinates (e.g., (x,y)) are used to indicate different positions on the chip. Users have the ability to maneuver the design to correspond to a region of a chip image through a user interface.
However, it is often difficult for a user to find correspondences between the image and the design layout that would allow the user to align the image and the layout. In a typical use case, the analytical tool shows a live image of a device under test (for example, an image reconstructed from reflected light) and the user tries to navigate to a desired feature that is known from the layout. In another case, the user has acquired a data image from the analytic tool and wants to determine where in the design layout a point of interest is located. In both of these cases, the user may be frustrated by the fact that circuit designs are often very large. In addition, the images acquired from an analytical tool can be visually very different from the original design layout, due to the former being represented in contrast and pixels, while the latter is represented as, e.g., ideal polygons.
In a typical alignment process, a user attempts to visually identify some unique features that are easy to locate in both an image of the device under test and the layout design. However, even for an expert user, identifying these correspondences is error prone, difficult, and time consuming.